The present invention relates to a method of forming a semiconductor memory device and, more particularly, to a method of forming a semiconductor memory device which can improve threshold voltage distributions of the semiconductor memory device.
Semiconductor memory devices can be classified based on construction, material and driving method. Flash memory devices have become increasing popular due to ease of operation and large memory capacity.
A flash memory device generally has a structure in which a tunnel insulating layer, a floating gate, a dielectric layer and a control gate are sequentially stacked over a semiconductor substrate. The floating gate is used as a charge trap layer. The floating gate is described in detail below.
The floating gate is formed of a conductive layer, preferably, polysilicon. Semiconductor memory devices of 40 nm or less generally use a p-type doped polysilicon layer. The polysilicon layer can be formed by a chemical vapor deposition (CVD) method. Specifically, the polysilicon layer can be formed by a thermal CVD method using SiH4 and PH3 gas. After the polysilicon layer is formed, a thermal treatment process for lowering the resistance of the polysilicon layer is carried out.
The thermal treatment process lowers the resistance of the polysilicon layer, but increases the size of a grain. In particular, with the high integration of semiconductor memory devices, strain in the grain size can change distributions of a subsequent threshold voltage. Consequently, the electrical properties of the semiconductor memory device may be degraded.